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| (R) CMOS MT8804A 8 x 4 Analog Switch Array Features * * * * * * * * * * Microprocessor compatible control inputs On chip control memory and address decoding Row addressing Master reset 32 crosspoint switches in 8 x 4 array 5.0V to 15.0V operation Low crosstalk between switches Low on resistance: 90 (typ.) at 13V Matched switch characteristics Switches frequencies up to 40MHz ISSUE 2 October 1989 Ordering Information MT8804AC 24 Pin Ceramic DIP MT8804AE 24 Pin Plastic DIP MT8804AP 28 Pin PLCC -40 to 85C Description The MT8804A is a CMOS/LSI 8 x 4 Analog Switch Array incorporating control memory (32 bits), decoder and digital logic level converters. This circuit has digitally controlled analog switches having very low "ON" resistance and very low "OFF" leakage current. Switches will operate with analog signals at frequencies to 40 MHz and up to 15.0Vp-p. A "HIGH" on the Master Reset input switches all channels "OFF" and clears the memory. This device is ideal for crosspoint switching applications. Applications * * * * PABX and key sytems Data acquisition systems Test equipment/instrumentation Analog/digital multiplexers AE D0 D1 D2 D3 VDD VEE VSS 1 1 **************** A0 A1 A2 8 32 3 to 8 Decoder 8x4 Latches Switch Array Li I/O (i=0-7) ******************* MR Ji I/O (i=0-3) Figure 1 - Functional Block Diagram 3-3 MT8804A CMOS 24 PIN CERDIP/PLASTIC DIP Figure 2 - Pin Connections Pin Description Pin #* 1-3 4 5 6 7 8 9 10 11 12 13 14-16 17 Name L2-L0 D0 J0 DI J1 D2 J2 D3 J3 VSS VEE A0-A2 AE Description L2-L0 Analog Lines (Inputs/Outputs): these are connected to the L2-L0 columns of the switch array. D0 Data (Input): Active High. J0 Analog Junctor (Input/Output): this is connected to the J0 row of the switch array. DI Data (Input). Active High. J1 Analog Junctor (Input/Output): this is connected to the J1 row of the switch array. D2 Data (Input): Active High. J2 Analog Junctor (Input/Output): this is connected to the J2 row of the switch array. D3 Data (Input): Active High. J3 Analog Junctor (Input/Output): this is connected to the J3 row of the switch array. Digital Ground Reference. Negative Power Supply. A0-A2 Address Lines (Inputs). Address Enable/Strobe (Input): enables function selected by address and data. Address must be stable before AE goes high and D0-D3 must be stable on the falling edge of the AE. Active High. Master RESET (Input): this is used to turn off all switches. Active High. L7-L3 Analog Lines (Inputs/Outputs): these are connected to the L7-L3 columns of the switch array. Positive Power Supply. 18 19-23 24 MR L7-L3 VDD * Plastic DIP and CERDIP only 3-4 D3 J3 VSS VEE A0 A1 NC L2 L1 L0 D0 J0 D1 J1 D2 J2 D3 J3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD L3 L4 L5 L6 L7 MR AE A2 A1 A0 VEE 4 3 2 1 28 27 26 * NC L0 L1 L2 VDD L3 L4 12 13 14 15 16 17 18 NC D0 J0 D1 J1 D2 J2 5 6 7 8 9 10 11 25 24 23 22 21 20 19 L5 L6 L7 MR AE A2 NC 28 PIN PLCC CMOS Functional Description The MT8804A is a CMOS/LSI 8 X 4 Analog Switch Array incorporating an 8 X 4 analog switch array, address decoder, control memory, and digital logic level converter. The analog switch array is arranged in 8 rows and 4 columns. The row input/outputs are referred to as Lines (L0-L7) and the column input/outputs as Junctors (J0-J3). The crosspoint analog switches interconnect the lines and junctors when turned "ON" and provide a high degree of isolation when turned "OFF". Interchannel crosstalk is minimal despite the high density of the analog switch array. The control memory of the MT8804A can be treated as an 8 word by 4 bit random access memory. The 8 words are selected by the ADDRESS (A0-A2) inputs through the on chip address decoder. Data is presented to the memory via the four DATA inputs (D0-D3). This data is asynchronously written into the control memory whenever the ADDRESS ENABLE (AE) input is HIGH. A HIGH level written into a memory cell turns the corresponding crosspoint switch "ON" while a LOW level causes the crosspoint to turn "OFF". Only the crosspoint switches corresponding to the addressed memory word are affected when data is written into the memory. The remaining switches retain their previous states. By establishing appropriate patterns in the control memory, any combination of lines and junctors may be interconnected. A HIGH level on the MASTER RESET (MR) input returns all memory locations to a LOW level and turns all crosspoint switches "OFF" effectively isolating the lines from the junctors. The digital logic level converters allow the digital input levels to differ from limits of the analog levels switched through the array. For example, with 8x8 Analog/Digital Switch Two MT8804s configured as shown, implement an 8 x 8 analog/digital switch. The switch capacity can be expanded to an M x N array of inputs/ outputs. Expansion in the M dimension is as shown with the MT8804A lines (L0-L7) commoned. Expansion in the N dimension is accomplished by replicating the circuit shown and connecting the MT8804A junctors (J0-J3) in common. The address and data control inputs of the MT8804A's can be connected in common for any size and switch provided that the address enable (AE) inputs are driven individually. A particular signal path is connected by setting up the appropriate signals or the address and data lines and taking the corresponding address enable input high. The master reset (MR), when taken high, disconnects all signal paths. MT8804A Figure 3 - On Resistance vs. Temperature (Input Signal Voltage=Supply Voltage/2) VDD=5V, V SS=0V and VEE=-6V, the control inputs can be driven by a 5V system while the analog voltages through the crosspoint switches can swing from +5V to -6V. Figure 4 - On Resistance vs. Input Signal Voltage Figure 5 - 8 x 8 Analog/Digital Switch 3-5 MT8804A CMOS Absolute Maximum Ratings* - Voltages are with respect to VEE unless otherwise stated. Parameter 1 Supply Voltage Symbol VDD-VSS VDD-VEE VSS-VEE VINA VIN I TS PLASTIC DIP CERDIP PD PD -65 Min -0.3 -0.3 -0.3 VEE-0.3 VSS-0.3 Max 16 16 16 VDD+0.3 VDD+0.3 10 +150 0.6 1.2 Units V V V V V mA C W W 2 3 4 5 6 Analog Input Voltage Digital Input Voltage Current on any Logic Pin Storage Temperature Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated. Characteristics 1 2 Operating Temperature Supply Voltage Sym TO VDD-V SS VDD-V EE VSS-VEE VINA VIN Min -40 5 5 0 VEE VSS Typ 25 5 10 5 Max 85 15 15 10 VDD VDD Units C V V V V V Test Conditions 3 4 Analog Input Voltage Digital Input Voltage DC Electrical Characteristics Characteristics 1 2 3 Quiescent Supply Current Off-state Leakage Current (Any line to any junctor) Input Logic "0" level Voltages are with respect to VEE=VSS=0V. Sym IDD IOFF VIL Min Typ 1 0.1 Max 100 500 3.0 1.5 Units A nA V V V V Test Conditions VDD=15V. All digital inputs at VIN=VSS or VDD VDD=13V, Switch is `Off' IVJi - VLjI = VDD - VEE VDD =10V VDD=5V VINA=VDD through 1k VDD =10V VDD=5V VINA=VDD through 1k VDD=13V 4 Input Logic "1" level VIH 7.0 3.5 8.0 5 Maximum current through Crosspoint Switch IMAX mA DC Electrical Characteristics are at ambient temperature (25C). Typical figures are for design aid only; not guaranteed and not subject to production testing. DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins. Characteristics 1 On-state VDD=13V Resistance VDD=10V VDD= 5V 2 Difference in on-state resistance between two switches VDD=13V VDD=10V 3-6 Sym Min R ON 60 25C Typ 90 105 290 Max 108 160 650 70C Typ 105 120 320 85C Typ 110 125 325 Units Test Conditions VSS=VEE=0V,VDC=VDD/2, IVJi - VLjI = 0.6V RON 20 30 20 30 20 30 VSS=VEE=0V,VDC=VDD/2, IVJi - VLjI = 0.6V CMOS MT8804A AC Electrical Characteristics - Crosspoint Performance -VDC is the external DC offset applied at the analog I/O pins. Voltages are with respect to VDD=10V, VSS=V EE=0V unless otherwise stated. Characteristics 1 2 3 4 Switch Line Capacitance Switch Junctor Capacitance Feedthrough Capacitance Frequency Response Channel "ON" 20LOG(VOUT / VINA) = -3dB Total Harmonic Distortion VDD=15V/VDC=7.5V VDD=10V/VDC=5V VDD=5V/VDC=2.5V Feedthrough Channel "OFF" Feed.=20LOG (VOUT / VINA) Crosstalk between any two channels for switches Li - Ji and Lj - Jj. Li - Ji is "ON" Lj - Jj is "OFF" Xtalk=20LOG (VJj/VLi). Propagation delay through switch Sym CIS COS CI F3dB Min Typ 5 20 0.2 40 Max Units pF pF pF MHz Test Conditions 5 THD 0.1 0.2 1.0 -50 % % % dB 6 FDT 7 Xtalk -40 dB Switch is "ON"; VDC=5V, VINA=5Vpp sinewave f= 1kHz; RL = 1k Switch is "ON"; VEE=VSS=0V VINA=5Vpp sinewave f= 1kHz; RL = 10k All Switches "OFF"; VINA= 5Vpp sinewave f= 1MHz; RL= 1k. VDC=5V VINA=2Vpp sinewave f= 1.0MHz; RL = 600. VINA=2Vpp sinewave f= 3.4kHz; RL = 600. VDC = 5V -90 dB 8 tPS 10 ns CL=50pF AC Electrical Characteristics are at ambient temperature (25C). Typical figures are for design aid only; not guaranteed and not subject to production testing. AC Electrical Characteristics - Control and I/O Timings- Voltages are with respect otherwise stated. to VSS=VEE=0V unless Characteristics 1 2 3 4 5 6 7 8 9 Digital Input Capacitance Setup Time D0-D3 to AE Hold Time D0-D3 to AE Setup Time Address to AE Hold Time Address to AE AE Pulse Width AE to Switch Status Delay DATA to Switch Status Delay MR to Switch Status Delay Sym CDI tDS tDH tAS tAH tAEW tPAE tPLH tPHL tMR tMRR Min 150 200 120 300 0 50 120 300 100 250 Typ 5 Max Units pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions VDD=10V VDD=10V VDD=5V VDD=10V VDD=5V VDD=10V VDD=5V VDD=10V VDD=5V VDD=10V VDD=5V VDD=10V VDD=5V VDD=10V VDD=5V VDD=10V VDD=5V VDD=10V VDD=5V 200 650 250 650 250 500 200 500 300 900 400 1000 400 600 350 750 See Note 1 See Note 1 See Note 2 AC Electrical Characteristics are at ambient temperature (25C). Typical figures are for design aid only; not guaranteed and not subject to production testing. Note 1 R L = 10k, C L=50pF Note 2 R L = 1k, C L =50pF Digital Input rise time (tr) and fall time (tf) = 5ns. 3-7 MT8804A CMOS 50% MR tAEW 50% tAS ADDRESS 50% 50% tAH D0-D3 50% tDS ON OFF tPLH /tPHL tPAE tPLH/tPHL tMR tDH 50% 50% 50% 50% AE SWITCH tMRR Figure 6 - Control Memory Timing Diagram Memory Reset MR 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Enable AE X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address A2 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Addressed Line A0 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Input Data To Control Memory D3 D2 X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Junctors Connected To Addressed Line D0 X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A1 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D1 X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 J3 J2 J1 J0 ALL NONE L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L1 X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 All Switches "OFF" No Change of State * * * * * * * * + + + + + + + + * * * * * + + + + * * * * + + + + * * * + + * * + + * * + + * * + + * * + * + * + * + * + * + * + * + * 0 0 1 1 0 0 0 1 1 0 L1 L2 1 0 1 0 1 0 1 0 + * + * + * + * 0 0 1 1 0 0 1 1 0 1 L2 L3 1 0 1 0 1 0 1 0 + * + * + * + * 0 0 1 1 0 1 1 0 1 0 L3 L4 1 0 1 0 1 0 1 0 + * + * + * + * 0 0 1 1 1 1 0 0 0 1 L4 L5 1 0 1 0 1 0 1 0 + * + * + * + * 0 0 1 1 1 1 0 1 1 0 L5 L6 1 0 1 0 1 0 1 0 + * + * + * + * 0 0 1 1 1 1 1 1 0 1 L6 L7 1 0 1 0 1 0 1 0 + * + * + * + * 0 1 1 1 1 L7 1 1 1 1 + + + + Table 1 - Address Decode Truth Table NOTES: 0 - Low Logic Level 1 - High Logic Level X - Don't Care Condition + - Indicates Connection Between Junctor and Addressed Line * - Indicates No Connection Between Junctor and Addressed Line 3-8 |
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